1. Field of the Invention
The present invention relates to semiconductor members and semiconductor devices which are useful for silicon-on-insulator (SOI) devices and to methods for manufacturing these semiconductor members and devices. Specifically, the present invention relates to semiconductor members and semiconductor devices which are capable of gettering heavy metal elements and to methods for manufacturing these semiconductor members and devices.
2. Description of the Related Art
Known semiconductor members include, for example, substrates having at least two laminated layers composed of different types of semiconductor materials and SOI substrates each composed of a semiconductor layer laminated on an insulating layer.
In bulk Si wafers, ultra-high purity crystals can be obtained by typical wafer manufacturing methods such as the Czpchralski process (CZ process), since segregation coefficients of heavy metal elements in Si crystals are very low.
In contrast, SOI wafers use bulk Si as a starting material and inevitably undergo a heat treatment process for the formation of an insulating layer or for the smoothing of the surface in any manufacturing method. In the heat treatment process, heavy metal elements contained in a furnace or in a heater tend to flow into the stream of a gas at high temperatures and possibly diffuse into an SOI wafer during its manufacture.
When ion implantation is used in the manufacture, a member in an evacuated housing or in the passage of implanted ions is irradiated with ions, the component elements of the member are ionized, and the resulting ions can be implanted into an SOI wafer during its manufacture, together with a principle ion to be implanted into the wafer.
Heavy metal elements entering in an Si crystal freely diffuse in the crystal during a treatment at high temperatures, but gradually become limited in diffusion in a cooling process, and are ultimately fixed by the formation of silicide compounds by a reaction with Si or the formation of oxides by a reaction with oxygen. For example, Ni and Cu are known to form silicides to thereby accumulate in the circumference of minute defects in the Si crystal, as described by Takao Abe in xe2x80x9cSilicon: Crystal Growth and Wafer Processingxe2x80x9d, pp. 233, Baifukan. Fe is also known to form a silicide in the interface between Si and SiO2 to thereby segregate when it diffuses in an Si crystal having an oxide film, as described in J. Appl. Phys., 83, 583 (1998).
Such heavy metal elements may form defects in Si crystals and may form deep levels in an Si band gap in some cases. If a defect is formed in a single-crystal semiconductor layer as an active device region, a chip manufactured in this region becomes defective. The formation of a deep level by such a heavy metal element causes changes in electrical properties of the chip to thereby decrease the yield of chips. The ratio of the defects or level-forming regions to the size of the device increases with further enhanced miniaturization and higher density packing of devices, and very strong demands have been made to remedy contamination with heavy metal elements.
Such a device manufacturing operation includes a number of processes, and it is difficult to always maintain all the processes under normal conditions. Accordingly, unexpected abnormalities may occur in some processes to thereby allow heavy metal elements to contaminate a wafer during its manufacture. It takes many days to manufacture devices, and if an abnormality in an intermediate process is found after finished devices are obtained, all the wafers in the manufacturing operation at that time potentially are defective.
To avoid this problem, in bulk Si wafers, a gettering site for gettering heavy metal elements is formed in the back or inside of the wafer to thereby prevent unexpected contamination of the wafer with heavy metal elements during the manufacturing process.
The following gettering techniques are well known and are effectively used to remove heavy metal elements from the active device region in the device process.
1. Gettering heavy metal elements inside the wafer by intrinsic gettering utilizing the precipitation of oxygen in Z wafers;
2. Gettering heavy metal elements in the back of the wafer by extrinsic gettering such as backside damage, the formation of a polysilicon film, and the diffusion of phosphorus.
SOI wafers are also starting materials of the device process as bulk Si, and in these wafers, increasing demands have been made to remedy contamination with heavy metal elements. SOI wafer fabricators have made intensive efforts to remedy heavy metal contamination mainly along a course to avoid contamination with heavy metal elements during the manufacturing process.
However, heavy metal element contamination, which may occur in the heat treatment process, cannot be significantly prevented, and the heavy metal contamination levels of all the product SOI wafers cannot be strictly ensured. Additionally, if the wafer is contaminated with heavy metal elements through the heat treatment or ion implantation during the manufacturing process of an SOI wafer, the SOI wafer must have a gettering site gettering these heavy metal elements.
Even if SOI wafers having a perfect crystal quality are manufactured, the chip yield may be decreased due to heavy metal element contamination when heavy metal elements contaminate the wafers in the heat treatment operation of the device process.
In SOI wafers, a semiconductor element or device such as a transistor is formed in a limited region, that is, an ultrathin single-crystal Si region on an insulating layer (oxide film). If this region is free from contamination with heavy metal elements and the oxide film as an insulating layer is uniformly formed, the chip yield can be prevented from decreasing due to heavy metal element contamination.
The manufacturing methods of SOI wafers are roughly classified under two groups: a separation by ion-implanted oxygen (SIMOX) process in which oxygen ions are implanted into an Si single-crystal substrate to thereby form an insulating layer; and a bonding process in which two different semiconductor substrates are bonded and a single-crystal semiconductor layer is formed by polishing or separation.
The oxide film (insulating layer) in the bonded SOI wafer is composed of a uniform thermal oxide film and is believed to have a higher quality than that of the oxide film of the SIMOX SOI wafer formed by oxygen ion implantation and annealing. Additionally, the SIMOX SOI wafer tends to have crystal defects in the single-crystal semiconductor layer induced by oxygen ion implantation. Accordingly, the bonding process is believed to more easily manufacture high-quality SOI wafers than the SIMOX process.
In the SIMOX process, it is known that oxidation induced stacking faults (OSFs) are formed immediately below the insulating layer simultaneously with the formation of the insulating layer. Cu and Ni, which may contaminate the wafer in the heat treatment process, are captured by OSFs, and the single-crystal semiconductor layer becomes resistant to heavy metal element contamination. This means that a gettering site is spontaneously formed without any extra process in the SIMOX manufacturing process and that the SIMOX process is superior in cost to the bonding process.
In the bonded SOI wafers, attempts have also been made to form a gettering site inside the substrate to thereby getter heavy metal elements.
For example, in a method described in Japanese Patent Laid-Open No. 6-163862, a layer in which a high concentration of phosphorus atoms is diffused, an ion implantation layer, or a lattice mismatching layer is formed on one of two substrates to be bonded, and the formed layer plays a role as a gettering site.
In a method described in Japanese Patent Laid-Open No. 8-293589, the substrate side of a wafer is subjected to a two-stage heat treatment to thereby form an oxygen precipitate, and dislocations are introduced in the vicinity of the surface of the wafer by heat stress in a cooling operation to form two gettering sites.
In a method described in Japanese Patent Laid-Open No. 8-116038, a layer in which phosphorus atoms are diffused in a high concentration on the back of a substrate plays a role as a gettering site.
Miao Zhang, et al., mention that, when a multiplicity of microcavities are formed in an SOI wafer by hydrogen or helium ion implantation and a subsequent heat treatment, the microcavities getter metal impurities. J. Appl. Phys., vol. 86, no. 8 (1999).
Such conventional SOI substrates will be illustrated below with reference to the drawings.
FIG. 16 is a sectional view showing an SOI substrate as a conventional semiconductor member.
SOI substrate 1 includes substrate 2 composed of a single-crystal semiconductor such as a silicon wafer, buried insulating layer 3 formed on substrate 2, and single-crystal semiconductor layer 4 composed of silicon formed on buried insulating layer 3. By ion implantation from the surface of SOI substrate 1 and heat treatment, a multiplicity of microcavities 6 is formed in layer region 5 having a predetermined depth from the upper interface of substrate 2.
FIG. 17 is a sectional view showing another conventional SOI substrate. In this SOI substrate, a multiplicity of microcavities 6 is formed in single-crystal semiconductor layer 4.
However, according to these conventional technologies, a heat treatment for gettering metal impurities by microcavities may destroy the microcavities to thereby invite cracking in the layer region having the microcavities in some cases.
In particular, the amount and location of microcavities formed by ion implantation and heat treatment depend on the implantation energy and dose of the implanted ion species, and the formed microcavities show a certain distribution in the range of implanted ions. Accordingly, the layer region having the microcavities has a large thickness, and a multiplicity of microcavities is formed so as to overlap with one another in the thickness direction in the layer region, thus deteriorating the mechanical strengths of the layer region. In some cases, microcavities are formed in unexpected areas, and metal impurities are captured by the formed microcavities, thus adversely affecting the manufacture and design of semiconductor devices.
When microcavities are formed after the formation of an SOI substrate, ions are implanted through the semiconductor layer to thereby invite defects to occur in the semiconductor layer.
As thus described, conventional technologies are still insufficient and must be improved to provide semiconductor members which are practical and have satisfactory characteristics.
Accordingly, an object of the present invention is to provide a semiconductor member and semiconductor device which are practical and have more satisfactory characteristics than conventional equivalents and to provide methods for manufacturing thus semiconductor member and semiconductor device.
Another object of the present invention is to provide a semiconductor member and semiconductor device which have a satisfactory gettering capability, which can prevent destruction of microcavities and can maintain the mechanical strengths of the semiconductor member and to provide methods for manufacturing thus semiconductor member and semiconductor device.
A further object of the present invention is to provide a method for manufacturing a semiconductor member, which method can easily form a gettering site.
Specifically, the present invention provides, in an aspect, a semiconductor member including a substrate, an insulating layer formed on the substrate, and a semiconductor layer formed on the insulating layer, and the semiconductor member includes a monolayer region having plural microgaps for gettering metal impurities, which plural microgaps are arranged along an interface inside the semiconductor member.
The interface is preferably an interface between the semiconductor layer and the insulating layer.
The interface is preferably a bonding interface.
Preferably, the insulating layer is a buried insulating layer formed on the substrate, the semiconductor layer is a single-crystal semiconductor layer formed on the buried insulating layer, and the interface is an interface between the single-crystal semiconductor layer and the buried insulating layer or an interface between the buried insulating layer and the substrate.
The concentration of Ni captured in the monolayer region is preferably equal to or less than 5xc3x971010 per square centimeter.
It is preferred that the insulating layer is a buried insulating layer formed on the substrate, the semiconductor layer is a single-crystal semiconductor layer formed on the buried insulating layer, and the lengths of the microgaps in the thickness direction are shorter than the thickness of the single-crystal semiconductor layer or of the buried insulating layer.
The microgaps are preferably box-shaped (rectangular) having a lengthwise side 10 nm to 100 nm long and a widthwise side 10 nm to 100 nm long in a plane substantially in parallel with the interface. Alternately, microgaps which are not box-shaped, have having an area equivalent to that of a box of the abovementioned dimensions.
The microgaps are preferably box-shaped having a lengthwise side and a widthwise side each substantially in parallel with the crystal orientations in a plane substantially in parallel with the interface.
The density of the microgaps in a plane along the interface is preferably in a range from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter.
The inner surfaces of the microgaps are preferably each coated with a film.
In another aspect, the present invention provides a method for manufacturing a semiconductor member, which semiconductor member includes a substrate, an insulating layer formed on the substrate, and a semiconductor layer formed on the insulating layer, and has a monolayer region having plural microgaps, which plural microgaps are arranged along an interface inside the semiconductor member. The method includes the steps of:
preparing a first substrate and a second substrate, which first substrate includes a transfer layer region having the semiconductor layer; and
transferring the transfer layer region from the first substrate to the second substrate. The transferring step includes a step of bonding the first substrate with the second substrate so as to interpose the plural microgaps for gettering metal impurities between the first substrate and the second substrate.
The interface is preferably an interface between the semiconductor layer and the insulating layer.
Preferably, one of the surface of the transfer layer region and the surface of the second substrate is an insulative surface, and the other is a semiconductor surface, and the bonding step includes a step of bringing these two surfaces into close contact with each other.
The bonding procedure is preferably performed under bonding conditions suitable to interpose the microgaps between surfaces to be bonded.
Under bonding conditions, it is preferred that the surfaces to be bonded are made hydrophobic, an oxidizing atmosphere is used as an atmosphere for bonding, and a heat treatment for improving a bonding strength is performed at a temperature equal to or higher than 900xc2x0 C.
Under bonding conditions, the temperature of the substrate at an early stage of epitaxial growth of the semiconductor layer is preferably set at 900xc2x0 C. to 1100xc2x0 C.
Under bonding conditions, the temperature of the substrate in a heat treatment for bonding is preferably set at 900xc2x0 C. to 1200xc2x0 C.
Under bonding conditions, the surfaces to be bonded are preferably cleaned with a solution containing hydrogen fluoride.
Under bonding conditions, the bonding procedure is performed in an atmosphere containing at least one of water and oxygen.
A substrate including a transfer layer region having a separation layer and the semiconductor layer formed on the separation layer is preferably prepared as the first substrate.
The separation layer is preferably a layer having relatively low mechanical strength.
The separation layer is preferably a porous layer formed by anodization.
Alternatively, the separation layer is preferably a layer formed by ion implantation.
The method preferably further includes a step of removing a portion of the first substrate other than the transfer layer region having the semiconductor layer.
The method preferably further includes, after the bonding step, a step of gettering metal impurities by the monolayer region having the plural microgaps arranged therein.
The method preferably includes a heat treatment in an inert atmosphere or reducing atmosphere as a step of gettering metal impurities by the monolayer region having the plural microgaps arranged therein.
The metal impurity may be at least one of Cr, Fe, Ni and Cu.
In a further aspect, the present invention provides a semiconductor device including a semiconductor member and a semiconductor element, which semiconductor member includes a substrate, a buried insulating layer formed on the substrate, and a single-crystal semiconductor layer formed on the buried insulating layer, and which semiconductor element is formed in the single-crystal semiconductor layer of the semiconductor member, in which the semiconductor member includes a monolayer region for gettering metal impurities, which monolayer region has plural microgap arranged along at least one interface of the buried insulating layer.
Preferably, metal impurities are captured by the monolayer region.
The metal impurities may be at least one of Cr, Fe, Ni and Cu.
Preferably, the semiconductor element is a fully depleted insulated gate transistor, and the microgaps are arranged along an interface between the buried insulating layer and the substrate.
Alternatively, it is preferred that the semiconductor element is a partially depleted insulated gate transistor, and the microgaps are arranged along an interface between the buried insulating layer and the substrate.
Alternatively, it is preferred that the semiconductor element is a partially depleted insulated gate transistor, and the microgaps are arranged along an interface between the buried insulating layer and the semiconductor layer.
In yet another aspect, the present invention provides a method for manufacturing a semiconductor device, which semiconductor device includes a semiconductor member and a semiconductor element, and the semiconductor member includes a substrate, a buried insulating layer formed on the substrate, and a single-crystal semiconductor layer formed on the buried insulating layer, and the semiconductor element is formed in the single-crystal semiconductor layer of the semiconductor member. This method includes the steps of forming the semiconductor element, and gettering metal impurities by a monolayer region at least during or after the forming step, which monolayer region has plural microgaps arranged along at least one interface of the buried insulating layer.
The present invention provides, in another aspect, a semiconductor member including a substrate, an insulating layer formed on the substrate, and a semiconductor layer formed on the insulating layer, in which plural microgaps for gettering metal impurities are arranged along an interface inside the semiconductor member so as not to overlap one another in the thickness direction of the semiconductor member.
The present invention provides, in a further aspect, a method for manufacturing a semiconductor member, which semiconductor member includes a substrate, an insulating layer formed on the substrate, and a semiconductor layer formed on the insulating layer, and plural microgaps for gettering metal impurities are arranged along an interface inside the semiconductor member so as not to overlap one another in the thickness direction of the semiconductor member. This method includes the steps of preparing a first substrate and a second substrate, which first substrate includes a transfer layer region having the semiconductor layer, and transferring the transfer layer region from the first substrate to the second substrate, in which the transferring step includes a step of bonding the first substrate with the second substrate so as to interpose the plural microgaps for gettering metal impurities between the first substrate and the second substrate.
The present invention provides, in yet another aspect, a semiconductor device including a semiconductor member and a semiconductor element, which semiconductor member includes a substrate, a buried insulating layer formed on the substrate, and a single-crystal semiconductor layer formed on the buried insulating layer, and which semiconductor element is formed in the single-crystal semiconductor layer of the semiconductor member, in which plural microgaps for gettering metal impurities are arranged along at least one interface of the buried insulating layer so as not to overlap one another in the thickness direction of the semiconductor member.
The present invention provides, in a still further aspect, a method for manufacturing a semiconductor device, which semiconductor device includes a semiconductor member and a semiconductor element, and the semiconductor member includes a substrate, a buried insulating layer formed on the substrate, and a single-crystal semiconductor layer formed on the buried insulating layer, and the semiconductor element is formed in the single-crystal semiconductor layer of the semiconductor member. This method includes the steps of forming the semiconductor element, and gettering metal impurities by plural microgaps at least during or after the forming step, which microgaps are arranged along an interface of the buried insulating layer so as not to overlap one another in the thickness direction of the semiconductor member.
The present invention provides, in still another aspect, a semiconductor member including a substrate, an insulating layer formed on the substrate, and a semiconductor layer formed on the insulating layer, in which plural microgaps having a length from 10 nm to 100 nm and a width from 10 nm to 100 nm are dispersed and arranged at a density from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter along a plane substantially in parallel with the surface of the semiconductor member.
In another aspect, the present invention provides a method for manufacturing a semiconductor member, which semiconductor member includes a substrate, an insulating layer formed on the substrate, and a semiconductor layer formed on the insulating layer, and in which plural microgaps having a length from 10 nm to 100 nm and a width from 10 nm to 100 nm are dispersed and arranged at a density from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter along a plane substantially in parallel with the surface of the semiconductor member. This method includes the steps of preparing a first substrate and a second substrate, which first substrate includes a transfer layer region having the semiconductor layer and transferring the transfer layer region from the first substrate to the second substrate, and the transferring step includes a step of bonding the first substrate with the second substrate so as to interpose the plural microgaps between the first substrate and the second substrate.
In a further aspect, the present invention provides a semiconductor device including a semiconductor member and a semiconductor element, which semiconductor member includes a substrate, a buried insulating layer formed on the substrate, and a single-crystal semiconductor layer formed on the buried insulating layer, and which semiconductor element is formed in the single-crystal semiconductor layer of the semiconductor member, in which plural microgaps having a length from 10 nm to 100 nm and a width from 10 nm to 100 nm are dispersed and arranged at a density from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter along at least one interface of the buried insulating layer.
In yet another aspect, the present invention provides a method for manufacturing a semiconductor device, which semiconductor device includes a semiconductor member and a semiconductor element, and the semiconductor member includes a substrate, a buried insulating layer formed on the substrate, and a single-crystal semiconductor layer formed on the buried insulating layer, and the semiconductor element is formed in the single-crystal semiconductor layer of the semiconductor member. This method includes the step of performing a heat treatment at least during or after a step of forming the semiconductor element, to thereby getter metal impurities by plural microgaps, which plural microgaps each have a length from 10 nm to 100 nm and a width from 10 nm to 100 nm and are dispersed and arranged at a density from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter along at least one interface of the buried insulating layer.
In still another aspect, the present invention provides a semiconductor member including a monolayer region for gettering metal impurities, which monolayer region has plural microgaps arranged along an interface inside the semiconductor member.
In a further aspect, the present invention provides a method for manufacturing a semiconductor member, which semiconductor member includes a monolayer region for gettering metal impurities, and which monolayer region has plural microgaps arranged along an interface inside the semiconductor member. This method includes the steps of preparing a first substrate and a second substrate, which first substrate includes a transfer layer region having a semiconductor layer, and transferring the transfer layer region from the first substrate to the second substrate, and the transferring step includes a step of bonding the first substrate with the second substrate so as to interpose the plural microgaps for gettering metal impurities between the first substrate and the second substrate.
The present invention provides, in another aspect, a semiconductor device including a semiconductor member and a semiconductor element, which semiconductor member includes a single-crystal semiconductor layer, and which semiconductor element is formed in the single-crystal semiconductor layer, and the semiconductor member further includes a monolayer region for gettering metal impurities, which monolayer region has plural microgaps arranged along at least one interface.
The present invention provides, in a further aspect, a method for manufacturing a semiconductor device, which semiconductor device includes a semiconductor member and a semiconductor element, and the semiconductor member has a single-crystal semiconductor layer, and the semiconductor element is formed in the single-crystal semiconductor layer. This method includes the steps of forming the semiconductor element, and gettering metal impurities by a monolayer region at least during or after the forming step, which monolayer region has plural microgaps arranged along an interface inside the semiconductor member.
The present invention provides, in yet another aspect, a semiconductor member including plural microgaps for gettering metal impurities, which plural microgaps are arranged along an interface inside the semiconductor member so as not to overlap one another in the thickness direction of the semiconductor member.
The present invention provides, in still another aspect, a method for manufacturing a semiconductor member, which semiconductor member includes plural microgaps arranged along an interface inside the semiconductor member so as not to overlap one another in the thickness direction of the semiconductor member. This method includes the steps of preparing a first substrate and a second substrate, which first substrate includes a transfer layer region having a semiconductor layer, and transferring the transfer layer region from the first substrate to the second substrate, and the transferring step includes a step of bonding the first substrate with the second substrate so as to interpose the plural microgaps for gettering metal impurities between the first substrate and the second substrate.
The present invention provides, in a still further aspect, a semiconductor device including a semiconductor member and a semiconductor element, which semiconductor member includes a single-crystal semiconductor layer, and which semiconductor element is formed in the single-crystal semiconductor layer, in which plural microgaps for gettering metal impurities are arranged along an interface inside the semiconductor member so as not to overlap one another in the thickness direction of the semiconductor member.
The present invention provides, in still another aspect, a method for manufacturing a semiconductor device, which semiconductor device includes a semiconductor member and a semiconductor element, and the semiconductor member includes a single-crystal semiconductor layer, and the semiconductor element is formed in the single-crystal semiconductor layer. This method includes the steps of forming the semiconductor element, and gettering metal impurities by plural microgaps at least during or after the forming step, which plural microgaps are arranged along an interface inside the semiconductor member so as not to overlap one another in the thickness direction of the semiconductor member.
In another aspect, the present invention provides a semiconductor member including plural microgaps, which plural microgaps each have a length from 10 nm to 100 nm and a width from 10 nm to 100 nm and are dispersed and arranged at a density from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter along a plane substantially in parallel with the surface of the semiconductor member.
In a further aspect, the present invention provides a method for manufacturing a semiconductor member, which semiconductor member includes plural microgaps, and the plural microgaps each have a length from 10 nm to 100 nm and a width from 10 nm to 100 nm and are dispersed and arranged at a density from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter along a plane substantially in parallel with the surface of the semiconductor member. This method includes the steps of preparing a first substrate and a second substrate, which first substrate includes a transfer layer region having a semiconductor layer, and transferring the transfer layer region from the first substrate to the second substrate, and the transferring step includes a step of bonding the first substrate with the second substrate so as to interpose the plural microgaps between the first substrate and the second substrate.
In still another aspect, the present invention provides a semiconductor device including a semiconductor member and a semiconductor element, which semiconductor member includes a single-crystal semiconductor layer, and which semiconductor element is formed in the single-crystal semiconductor layer, in which plural microgaps having a length from 10 nm to 100 nm and a width from 10 nm to 100 nm are dispersed and arranged at a density from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter along at least one interface.
In addition and advantageously, the present invention provides a method for manufacturing a semiconductor device, which semiconductor device includes a semiconductor member and a semiconductor element, and the semiconductor member includes a single-crystal semiconductor layer, and the semiconductor element is formed in the single-crystal semiconductor layer. This method includes the step of performing a heat treatment at least during or after a step of forming the semiconductor element, to thereby capture metal impurities by plural microgaps, which plural microgaps each have a length from 10 nm to 100 nm and a width from 10 nm to 100 nm and are dispersed and arranged at a density from 5xc3x97109 per square centimeter to 5xc3x971011 per square centimeter along at least one interface.
Further objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments with reference to the attached drawings.